1. Field of the Invention
The present invention relates to an adjustment system for adjusting a phase/frequency detecting device in a phase locked loop, and more particularly, the present invention relates to a phase/frequency detecting device and method that can reduce the glitch disturbance.
2. Description of the prior art
Referring to FIG. 1, FIG. 1 is a schematic diagram of a conventional phase locked loop 10. The conventional phase locked loop 10 comprises a phase/frequency detecting device 12, a charge pump 40, a voltage-controlled oscillator 42, and a divider 44. The conventional phase/frequency detecting device 12 has a pair of flip flops (not shown) and is used for comparing a target clock signal 20, which is generated from the phase locked loop 10, with a predetermined reference clock signal 22, and outputting a set of control signals 26, 28 to further control the target clock signal 20 so as to synchronize with the reference clock signal 22.
The charge pump 40 is used for receiving the set of control signals 26, 28 outputted from the phase/frequency detecting device 12, and outputting a control voltage 46. The voltage-controlled oscillator 42 is used for generating a corresponding data clock signal 48 according to the control voltage 46. The divider 44 is used for dividing the frequency of the data clock signal 48 by a predetermined divisor and then generating the target clock signal 20. By the above-mentioned procedures, the phase/frequency detecting device 12 continuously compares the target clock signal 20 with the reference clock signal 22 and continuously outputs the set of control signals 26, 28 for continuously generating the target clock signal 20 to synchronize with the reference clock signal 22.
Referring to FIG. 2, FIG. 2 is a time-sequence diagram of the phase locked loop shown in FIG. 1. In FIG. 2, the horizontal axis represents the time axis, and the vertical axis represents the signal amplitude. In the beginning, there is a phase difference P between the target clock signal 20 and the reference clock signal 22. When a glitch 16 occurs in the target clock signal 20 or the reference clock signal 22, the control signals 26, 28 outputted from the phase/frequency detecting device 12 are changed by the disturbance of the glitch 16; the disturbed control signals 26, 28 show that there is another phase difference Q between the target clock signal 20 and the reference clock signal 22. However, there is only one phase difference P between the target clock signal 20 and the reference clock signal 22. Thus, the phase/frequency detecting device 12 often misinterprets the phase difference between the target clock signal 20 and the reference clock signal 22 and outputs a set of disturbed control signals 26, 28. Through the above-mentioned procedures, this disturbed set of control signals 26, 28 further generates another corresponding target clock signal 20; therefore the original operation is greatly disturbed.
It is still impossible to fully forecast and prevent when, where, and how the glitch 16 is generated. On the other hand, the conventional phase locked loop 10 merely uses the phase/frequency detecting device 12 and the feedback control circuit 18 to control the target clock signal 20 for synchronizing with the reference clock signal 22. When a glitch 16 is generated, or when the phase difference between the target clock signal 20 and the reference clock signal 22 becomes larger, the phase/frequency detecting device 12 usually takes longer time to synchronize the target clock signal 20 and the reference clock signal 22.
Therefore, the objective of the present invention is to provide an adjustment system and the method for adjusting the phase/frequency detecting device 12, in order to solve the problem mentioned above.